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| INTEGRATED CIRCUITS PCK953 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver Product specification Supersedes data of 2000 Oct 25 ICL03 -- PC Motherboard ICs; Logic Products Group 2001 Feb 08 Philips Semiconductors Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter. The PCK953 has a differential LVPECL reference input, along with an external feedback input. These features make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide LVCMOS levels with the ability to drive terminated 50 transmission lines. For series terminated 50 lines, each of the PCK953 outputs can drive two traces, giving the device an effective fanout of 1:18. The device is packaged in a 7 x 7 mm 32-lead LQFP package to provide the optimum combination of board density and performance. PIN CONFIGURATION 32 VCO_SEL 31 BYPASS 30 PLL_EN 29 GNDO 25 GNDO 24 Q1 23 VCCO 22 Q2 21 GNDO 20 Q3 19 VCCO 18 Q4 17 GNDO MR/OE 10 Q7 12 GNDO 13 Q6 14 V CCO 15 V CCO 11 Q5 16 9 27 V CCO 28 QFB VCCA FB_CLK NC NC NC NC GNDI PECL_CLK 1 2 3 4 5 6 7 8 PECL_CLK 26 Q0 SW00625 FEATURES * Fully integrated PLL * Output frequency up to 125 MHz in PLL mode * Outputs disable in high impedance * LQFP packaging * 55 ps cycle-to-cycle jitter typical * 9 mA quiescent current, ICCA, typical * 60 ps static phase offset typical * Less than 10 A quiescent current, lCCO, typical ORDERING INFORMATION PACKAGES plastic low profile quad flat package; 32 leads TEMPERATURE RANGE 0 to +70C ORDER CODE PCK953BD DRAWING NUMBER SOT358-1 LOGIC DIAGRAM QFB PECL_CLK PECL_CLK PHASE DETECTOR FB_CLK LPF VCO 200-500 MHz B2 B4 Q7 7 Q0:6 VCO_SEL BYPASS MR/OE PLL_EN SW00624 2001 Feb 08 2 853-2222 25600 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 FUNCTION TABLE BYPASS 1 0 MR/OE 1 0 VCO_SEL 1 0 PLL_EN 1 0 Function PLL Enabled PLL Bypass Function Outputs Disabled Outputs Enabled Function B2 B1 Function Select VCO Select PECL_CLK ABSOLUTE MAXIMUM RATINGS1 SYMBOL VCC VI IIN Tstg Supply voltage Input voltage Input current Storage temperature range PARAMETER MIN -0.3 -0.3 -- -40 MAX 4.6 VDD+0.3 20 +125 UNIT V V mA C NOTE: 1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. 2001 Feb 08 3 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 DC CHARACTERISTICS Tamb = 0 to 70C; VCC = 3.3 V 5% SYMBOL VIH VIL Vp-p VCMR VOH VOL IIN CIN CPD ICC ICCPLL PARAMETER Input HIGH voltage LVCMOS inputs Input LOW voltage LVCMOS inputs Peak-to-peak input voltage Common mode range Output HIGH voltage Output LOW voltage Input current Input capacitance Power dissipation capacitance Maximum quiescent supply current Maximum PLL supply current per output All VCC pins VCCA pin only PECL_CLK PECL_CLK Note 1 IOH = -20 mA;2 IOL = 20 mA;2 CONDITION MIN 2.0 -- 300 VCC-1.5 2.4 -- -- -- -- -- -- TYP -- -- -- -- -- -- -- -- 25 9 9 MAX 3.6 0.8 1000 VCC-0.6 -- 0.5 75 4 -- 20 20 UNIT V V mV mV V V A pF pF mA mA NOTES: 1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input swing lies within the VPP specification. 2. The PCK953 outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications info section). PLL INPUT REFERENCE CHARACTERISTICS Tamb = 0 to 70C SYMBOL fref frefDC PARAMETER Reference input frequency Reference input duty cycle CONDITION MIN 20 25 MAX 125 75 UNIT MHz % NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider. AC CHARACTERISTICS Tamb = 0 to 70C; VCC = 3.3 V 5% SYMBOL tr, tf tpw tsk(O) fVCO fMAX PARAMETER Output rise/fall time Output duty cycle Output-to-output skews (relative to QFB) PLL VCO lock range Maximum output frequency PLL mode Bypass mode tpd(lock) tpd(bypass) tPLZ-HZ tPZL tjitter tlock Input to EXT_FB delay (with PLL locked) Input to Q delay Output disable time Output enable time Cycle-to-cycle jitter (peak-to-peak) Maximum PLL lock time fref = 50 MHz PLL bypassed -75 3 -- -- -- -- -- 5.2 -- -- 55 0.01 VCO_SEL = 1 VCO_SEL = 0 CONDITION 0.8 V to 2.0 V MIN 0.30 45 -- 200 20 50 TYP 0.55 50 -- -- -- MAX 0.8 55 100 500 100 125 225 125 7 7 6 100 10 UNIT ns % ps MHz MHz MHz MHz ps ns ns ns ps ms NOTE: 1. X will be targeted for 0 ns, but may vary from target by 150 ps based on characterization of silicon. 2001 Feb 08 4 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 APPLICATION INFORMATION Power supply filtering The PCK953 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The PCK953 provides separate power supplies for the output buffers (VCCO) and the phase-locked loop (VCCA) of the device. The purpose of this design technique is to try to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the PCK953. Figure 1 illustrates a typical power supply filter scheme. The PCK953 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the PCK953. From the datasheet, the IVCCA current (the current sourced though the VCCA pin) is typically 15 mA (20 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCCA pin, very little DC voltage drop can be tolerated when a 3.3 V VCC supply is used. The resistor shown in Figure 1 must have a resistance of 10-15 to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive, and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. It is recommended that the user start with an 8-10 resistor to avoid potential VCC drop problems, and only move to the higher value resistors when a higher level of attenuation is shown to be needed. Driving transmission lines The PCK953 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 , the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current, and thus only a single terminated line can be driven by each output of the PCK953 clock driver. For the series terminated case, however, there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 2 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the PCK953 clock driver is effectively doubled due to its capability to drive multiple lines. PCK953 OUTPUT BUFFER IN 14 RS = 36 ZO = 50 OutA PCK953 OUTPUT BUFFER IN 14 RS = 36 RS = 36 ZO = 50 OutB0 ZO = 50 OutB1 SW00627 3.3 V Figure 2. Single versus dual transmission lines The waveform plots of Figure 3 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the PCK953 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCK953. The output waveform in Figure 3 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (ZO / (RS + RO + ZO)) ZO = 50 o 50 RS = 36 o 36 RO = 14 VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31 V 5 RS = 5-15 PLL_VCC 22 F PCK953 VCC 0.01 F 0.01 F SW00626 Figure 1. Power supply filter Although the PCK953 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. 2001 Feb 08 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 At the load end, the voltage will double due to the near unity reflection coefficient, to 2.62 V. It will then increment towards the quiescent 3.0 V in steps separated by one round-trip delay (in this case 4.0 ns). with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 4 should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. 3.0 OutA tD = 3.8956 PCK953 OutB tD = 3.9386 OUTPUT BUFFER 14 RS = 22 2.5 ZO = 50 2.0 VOLTAGE (V) In 1.5 RS = 22 ZO = 50 1.0 0.5 14 + 22 o 22 = 50 o 50 25 = 25 SW00629 0 2 4 6 8 10 12 14 Figure 4. Optimized dual line termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition, IV characteristics are in the process of being generated to support the other board-level simulators in general use. TIME (ns) SW00630 Figure 3. Single versus dual waveforms Since this step is well above the threshold region, it will not cause any false clock triggering, however designers may be uncomfortable 2001 Feb 08 6 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1 2001 Feb 08 7 Philips Semiconductors Product specification 50-125 MHz PECL input/CMOS output 3.3 V PLL clock driver PCK953 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Date of release: 02-01 Document order number: 9397 750 08062 Philips Semiconductors 2001 Feb 08 8 |
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